UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 96

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
3.4.9
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/JG3-H and V850ES/JH3-H.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM) (V850ES/JG3-H only)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related
registers after setting the above registers.
(a) System wait control register (VSWC)
(b) On-chip debug mode register (OCDM) (V850ES/JG3-H only)
(c) Watchdog timer mode register 2 (WDTM2)
Cautions
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The V850ES/JG3-
H and V850ES/JH3-H require wait cycles according to the operating frequency. Set the following value to the
VSWC register in accordance with the frequency used.
The VSWC register can be read or written in 8-bit units.
Reset sets this register to 77H.
For details, see CHAPTER 32 ON-CHIP DEBUG FUNCTION.
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register to
activate this operation.
For details, see CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2.
VSWC
After reset:
Operating Frequency (f
f
16.6 MHz ≤ f
25 MHz ≤ f
33.3 MHz ≤ f
77H
CPU
< 16.6 MHz
R/W
CPU
CPU
CPU
< 33.3 MHz
< 25 MHz
≤ 48 MHz
Address:
CPU
)
FFFFF06EH
Set Value of VSWC
00H
01H
11H
12H
Number of Waits
0 (no waits)
CHAPTER 3 CPU FUNCTION
1
2
3
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