UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1077

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Next, the procedure of a SETUP transaction that uses IN/OUT tokens is explained below.
(a) When IN token is used (except a request automatically executed by hardware)
(b) When OUT token is used (except a request automatically executed by hardware)
FW should be used to clear the PROT bit of the UF0IS1 register to 0 after receiving the CPUDEC interrupt and
before reading data from the UF0E0ST register. Next, perform processing in accordance with the request and,
if it is necessary to return data by an IN token, write data to the UF0E0W register. Confirm that the PROT bit of
the UF0IS1 register is 0 after writing has been completed, and set the E0DED bit of the UF0DEND register to 1.
The hardware sends out data at the first IN token after the EP0NKW bit has been set to 1. If the PROT bit of
the UF0IS1 register is 1, it indicates that a SETUP transaction has occurred again before completion of control
transfer. In this case, clear the PROT bit of the UF0IS1 register to 0 by clearing the PROTC bit of the UF0IC1
register to 0, and then read data from the UF0E0ST register again. A request received later can be read.
FW should be used to clear the PROT bit of the UF0IS1 register after receiving the CPUDEC interrupt and
before reading data from the UF0E0ST register. Confirm that the PROT bit of the UF0IS1 register is 0 before
reading data from the UF0E0R register. If the PROT bit is 1, it means that invalid data is retained. Clear the
FIFO by FW (the EP0NKR bit is automatically cleared to 0). If the PROT bit of the UF0IS1 register is 0, read
the data of the UF0E0L register and read as many data from the UF0E0R register as set. When reading data
from the UF0E0R register has been completed (when the counter of the UF0E0R register has been cleared to
0), the hardware automatically clears the EP0NKR bit to 0.
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
Page 1077 of 1509