UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 988

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UPD70F3771GF-GAT-AX

Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet

Specifications of UPD70F3771GF-GAT-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-H, V850ES/JH3-H
20.9.5 Multi buffer receive block function
sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message
buffer type. These message buffers can be allocated in any area in the message buffer memory, and they are not
necessarily to be allocated adjacent to each other.
same ID is set to each message buffer. If the first message whose ID matches an ID of the message buffers is received, it
is stored in message buffer 10. At this point, the DN bit of message buffer 10 is set, prohibiting overwriting the message
buffer.
message with a matching ID is received, it is sequentially (in the ascending order) stored in message buffers 12, 13, and
so on. Even when a data block consisting of multiple messages is received, the messages can be stored and received
without overwriting the previously received matching-ID data.
buffer. For example, if a data block consists of k messages, k message buffers are initialized for reception of the data
block. The IE bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the IE bit in message buffer k-1 is
set to 1 (interrupts enabled). In this case, a reception completion interrupt occurs when a message has been received and
stored in message buffer k-1, indicating that MBRB has become full. Alternatively, by clearing the IE bit of message
buffers 0 to (k-3) and setting the IE bit of message buffer k-2, a warning that MBRB is about to overflow can be issued.
storing data in a single message buffer.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers
Suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and the
When the next message with a matching ID is received, it is received and stored in message buffer 11. Each time a
Whether a data block has been received and stored can be checked by setting the C0MCTRLm.IE bit of each message
The basic conditions of storing receive data in each message buffer for the MBRB are the same as the conditions of
Cautions 1. MBRB can be configured for each of the same message buffer types.
Remark
2. MBRB does not have a ring buffer structure. Therefore, after a message is stored in the message
3. MBRB operates based on the reception and storage conditions; there are no settings dedicated to
4. With MBRB, “matching ID” means “matching ID after mask”. Even if the ID set to each message
5. Priority among each MBRB conforms to the priority shown in 20.9.1 Message reception.
m = 00 to 31
message buffer of another MBRB whose ID matches but whose message buffer type is different
has a vacancy, the received message is not stored in that message buffer, but instead discarded.
buffer having the highest number in the MBRB configuration, a newly received message will no
longer be stored in the message buffer in the order from the lowest message buffer number.
MBRB, such as function enable bits. By setting the same message buffer type and ID to two or
more message buffers, MBRB is automatically configured.
buffer is not the same, if the ID that is masked by the mask register matches, it is considered a
matching ID and the buffer that has this ID is treated as the storage destination of a message.
CHAPTER 20 CAN CONTROLLER
Therefore, even if a
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