UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 878

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
19.16.1 Master operation in single master system
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Note Release the I
Remarks 1. For the transmission and reception formats, comply with the specifications of the communicating
communicating product. For example, when the EEPROM
SCL0n pin to the output port and output clock pulses from that output port until the SDA0n pin becomes
constantly high level.
2. n = 0 to 2, m = 0, 1
product.
2
C0n bus (SCL0n, SDA0n pins = high level) in compliance with the specifications of the
No
No
Figure 19-18. Master Operation in Single Master System
ACKEn = WTIMn = SPIEn = 1
Set STCENn, IICRSVn = 0
Transfer completed?
Initialize I
interrupt occurred?
interrupt occurred?
interrupt occurred?
OCKSm ← XXH
IICCLn ← XXH
SVAn ← XXH
IICCn ← XXH
STCENn = 1?
IICXn ← 0XH
IICFn ← 0XH
ACKDn = 1?
ACKDn = 1?
Restarted?
TRCn = 1?
Write IICn
Write IICn
IICEn = 1
Set ports
SPTn = 1
STTn = 1
INTIICn
INTIICn
INTIICn
START
2
C bus
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note
Waiting for stop condition detection
Yes
No
No
No
No
No
No
Communication start preparation
(stop condition generation)
Refer to Table 4-20 Settings When Port Pins Are Used for Alternate Functions
to set the I
Transfer clock selection
Local address setting
Start condition setting
Communication start preparation
(start condition generation)
Communication start
(address, transfer direction specification)
Waiting for ACK detection
Transmission start
Waiting for data transmission
SPTn = 1
2
END
C mode before this function is used.
TM
outputs a low level to the SDA0n pin, set the
Transfer completed?
WTIMn = WRELn = 1
interrupt occurred?
interrupt occurred?
WRELn = 1
ACKEn = 1
ACKEn = 0
WTIMn = 0
Read IICn
INTIICn
INTIICn
Yes
Yes
Yes
No
No
No
Reception start
Waiting for
data reception
Waiting for ACK detection
CHAPTER 19 I
Page 878 of 1509
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C BUS