UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 911

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(5) Recovery from bus-off state
When the CAN module is in the bus-off state, the transmission pins (CTXD0) cut off from the CAN bus always
output the recessive level.
The CAN module recovers from the bus-off state in the following bus-off recovery sequence.
<1> Request to enter the CAN initialization mode
<2> Request to enter a CAN operation mode
(a) Recovery from bus-off state through normal recovery sequence
The CAN module first issues a request to enter the initialization mode (refer to timing <1> in Figure 20-17).
This request will be immediately acknowledged, and the C0CTRL.OPMODE2 to OPMODE0 bits are cleared to
000B. Processing such as analyzing the fault that has caused the bus-off state, re-defining the CAN module
and message buffer using application software, or stopping the operation of the CAN module can be
performed by clearing the C0GMCTRL.GOM bit to 0.
Next, the module requests to change the mode from the initialization mode to an operation mode (refer to
timing <2> in Figure 20-17). This starts an operation to recover the CAN module from the bus-off state. The
conditions under which the module can recover from the bus-off state are defined by the CAN protocol ISO
11898, and it is necessary to detect 11 consecutive recessive-level bits more than 128 times. At this time, the
request to change the mode to an operation mode is held pending until the recovery conditions are satisfied.
When the recovery conditions are satisfied (refer to timing <3> in Figure 20-17), the CAN module can enter
the operation mode it has requested. Until the CAN module enters this operation mode, it stays in the
initialization mode. Whether the CAN module has completed transition to any other operation mode can be
confirmed by reading the OPMODE2 to OPMODE0 bits. Before transition to any other operation mode is
completed, OPMODE2 to OPMODE0 bits = 000B is read.
During the bus-off period and bus-off recovery sequence, the C0INFO.BOFF bit stays set (to 1). In the bus-off
recovery sequence, the reception error counter (C0ERC.REC0 to C0ERC.REC6) counts the number of times
11 consecutive recessive-level bits have been detected on the bus. Therefore, the recovery state can be
checked by reading the REC0 to REC6 bits.
Cautions 1. If a request to change the mode from the initialization mode to any operation mode to
(a) Recovery operation through normal recovery sequence
(b) Forced recovery operation that skips recovery sequence
2. In the bus-off recovery sequence, the REC0 to REC6 bits counts up (+1) each time 11
execute the bus-off recovery sequence again during a bus-off recovery sequence, the
bus-off recovery sequence starts from the beginning and 11 contiguous recessive bits
are counted 128 times again on the bus.
consecutive recessive-level bits have been detected. Even during the bus-off period, the
CAN module can enter the CAN sleep mode or CAN stop mode. To be released from the
bus-off state, the module must enter the initialization mode once. If the module is in the
CAN sleep mode or CAN stop mode, however, it cannot directly enter the initialization
mode. In this case, the bus off recovery sequence is started at the same time as the
CAN sleep mode is released even without shifting to the initialization mode. In addition
to clearing the C0CTRL.PSMODE1 and C0CTRL.PSMODE0 bits by software, the bus off
recovery sequence is also started due to wakeup by dominant edge detection on the
CAN bus (While the CAN clock is supplied, the C0CTRL.PSMODE0 bit must be cleared by
software after a dominant edge is detected.) .
CHAPTER 20 CAN CONTROLLER
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