UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1094

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Bit position
4
3
2
1
0
E0ODT
SUCES
STG
PROT
CPUDEC
Bit name
This bit indicates that data has been correctly received in the UF0E0R register.
This bit is automatically set to 1 by hardware when data has been correctly received. At
the same time, the EP0R bit of the UF0EPS0 register is also set to 1. If a Null packet has
been received, this bit is not set to 1. It is automatically cleared to 0 by hardware when
the FW reads the UF0E0R register and the value of the UF0E0L register becomes 0.
This bit indicates that either an FW-processed or hardware-processed request has been
received and that the status stage has been correctly completed.
This bit is set to 1 upon completion of the status stage. It is automatically cleared to 0 by
hardware when the next SETUP token is received.
This bit is also set to 1 when data with Data PID of 0 (Null data) is received in the status
stage of control transfer.
This bit is set to 1 when the stage of control transfer has changed to the status stage. It is
valid for both FW-processed and hardware-processed requests. This bit is also set to 1
when the stage of control transfer (without data) has changed to the status stage.
This bit is automatically cleared to 0 by hardware when the next SETUP token is received.
It is also set to 1 when the stage of control transfer has changed to the status stage while
ACK cannot be correctly received in the data stage. In this case, the EP0NKW bit of the
UF0E0N register is also cleared to 0 as soon as the UF0E0W register has been cleared,
if the FW is processing control transfer (read).
This bit indicates that a SETUP token has been received. It is valid for both FW-
processed and hardware-processed requests.
This bit is set to 1 when data has been correctly received in the UF0E0ST register. Clear
this bit to 0 by FW when the first read access is made to the UF0E0ST register. If it is not
cleared to 0 by FW, reception of the next SETUP token cannot be correctly recognized.
This bit is used to accurately recognize that a SETUP transaction has been executed
again during control transfer. If the SETUP transaction is re-executed during control
transfer and if a second request is executed by hardware, the CPUDEC bit is not set to 1,
but the PROT bit can be used for recognition of the re-execution.
This bit indicates that the UF0E0ST register has a request that is to be decoded by FW.
This bit is automatically cleared to 0 by hardware when all the data of the UF0E0ST
register is read.
1: Data is in UF0E0R register (interrupt request is generated).
0: Data is not in UF0E0R register (default value).
1: Control transfer has been correctly processed (interrupt request is generated).
0: Control transfer has not been processed correctly (default value).
1: Status stage (interrupt request is generated)
0: Not status stage (default value)
1: SETUP token is correctly received (interrupt request is generated).
0: SETUP token is not received (default value).
1: Data is in UF0E0ST register (interrupt request is generated).
0: Data is not in UF0E0ST register (default value).
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
Function
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