UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 610

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
11.4.4 Operation to rewrite register with transfer function
registers has a buffer register.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The following seven registers are provided with a transfer function and are used to control a motor. Each of the
• TAB1CCR0: Register that specifies the cycle of the 16-bit counter (TAB)
• TAB1CCR1: Register that specifies the duty factor of TOAB1T1 (U) and TOAB1B1 (U)
• TAB1CCR2: Register that specifies the duty factor of TOAB1T2 (V) and TOAB1B2 (V)
• TAB1CCR3: Register that specifies the duty factor of TOAB1T3 (W) and TOAB1B3 (W)
• TAB1OPT1: Register that specifies the culling of interrupts
• TAA4CCR0: Register that specifies the A/D conversion start trigger generation timing (TAA4 during tuning operation)
• TAA4CCR1: Register that specifies the A/D conversion start trigger generation timing (TAA4 during tuning operation)
The following three rewrite modes are provided in the registers with a transfer function.
• Anytime rewrite mode
• Batch rewrite mode (transfer mode)
• Intermittent batch rewrite mode (transfer culling mode)
This mode is set by setting the TAB1OPT0.TAB1CMS bit to 1. The specification of the TAB1OPT2.TAB1RDE bit is
ignored.
In this mode, each compare register is updated independently, and the value of the compare register is updated as
soon as a new value is written to it.
This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits
to 00000, and the TAB1OPT2.TAB1RDE bit to 0.
When data is written to the TAB1CCR1 register, data in the seven registers are transferred to the buffer register all at
once at the next transfer timing. Unless the TAB1CCR1 register is rewritten, the transfer operation is not performed
even if the other six registers are rewritten.
The transfer timing is the timing of each crest (match between the 16-bit counter value and TAB1CCR0 register value)
and valley (match between the 16-bit counter value and 0001H) regardless of the interrupt.
This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0 and setting the TAB1OPT2.TAB1RDE bit to 1.
When data is written to the TAB1CCR1 register, data from the seven registers is transferred to the buffer register all at
once at the next transfer timing. Unless the TAB1CCR1 register is rewritten, the transfer operation is not performed
even if the other six registers are rewritten.
If interrupt culling is specified by the TAB1OPT1 register, the transfer timing is also culled as the interrupts are culled,
and data from the seven registers is transferred all at once at the culled timing of the crest interrupt (match between
the 16-bit counter value and TAB1CCR0 register value) or valley interrupt (match between the 16-bit counter value
and 0001H).
For details of the interrupt culling function, see 11.4.3 Interrupt culling function.
CHAPTER 11 MOTOR CONTROL FUNCTION
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