UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 771

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Notes 1. If the CFnSCE bit is read while it is 1, the next communication operation is started.
Caution Be sure to clear bits 3 and 2 to “0”.
CFnSCE
• In master mode
• In slave mode
[Usage of CFnSCE bit]
• In single reception mode
• In continuous reception mode
This bit enables or disables the communication start trigger.
(a) In single transmission or transmission/reception mode, or continuous
(b) In single reception mode
(c) In continuous reception mode
This bit enables or disables the communication start trigger.
Set the CFnSCE bit to 1.
<1>When reception of the last data is completed by INTCFnR interrupt
<2>After confirming the CFnSTR.CFnTSF bit = 0, clear the CFnRXE bit to 0 to
<1>Clear the CFnSCE bit to 0 during reception of the last data by INTCFnR
<2>Read the CFnRX register.
<3>Read the last reception data by reading the CFnRX register after
<4>After confirming the CFnSTR.CFnTSF bit = 0, clear the CFnRXE bit to 0 to
0
1
transmission or continuous transmission/reception mode
A communication operation can be started by writing data to the CFnTX
register when the CFnSCE bit is
Set the CFnSCE bit to 1.
Disable starting the next receive operation by clearing the CFnSCE bit to 0
before reading the last receive data, because a receive operation is started by
reading receive data (CFnRX register)
Clear the CFnSCE bit to 0 one communication clock before reception of the
last data is completed to disable the start of reception after the last data is
received
servicing, clear the CFnSCE bit to 0 before reading the CFnRX register.
disable reception.
To continue reception, set the CFnSCE bit to 1 to start the next reception
by dummy-reading the CFnRX register.
interrupt servicing.
acknowledging the CFnTIR interrupt.
disable reception.
To continue reception, set the CFnSCE bit to 1 to wait for the next reception
by dummy-reading the CFnRX register.
2. The CFnSCE bit is not cleared to 0 one communication clock before the completion
Communication start trigger invalid
Communication start trigger valid
of the last data reception, the next communication operation is automatically
started.
Note 2
.
Specification of start transfer disable/enable
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
1.
Note 1
.
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