UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1391

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
32.1.3 Maskable functions
functions are listed below.
32.1.4 Register
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Reset, NMI, INTWDT2, WAIT, and HLDRQ signals can be masked.
The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JG3-H and V850ES/JH3-H
(1) On-chip debug mode register (OCDM) (V850ES/JG3-H only)
The OCDM register is used to select the normal operation mode or on-chip debug mode. This register is a special
register and can be written only in a combination of specific sequences (see 3.4.8 Special registers).
This register is also used to specify whether a pin provided with an on-chip debug function is used as an on-chip
debug pin or as an ordinary port/peripheral function pin. It also is used to disconnect the internal pull-down resistor
of the P56/INTP05/DRST pin.
The OCDM register can be written only while a low level is input to the DRST pin.
This register can be read or written in 8-bit or 1-bit units.
NMI0
NMI2
STOP
HOLD
RESET
WAIT
Maskable Functions with ID850QB
Table 32-2. Maskable Functions
NMI pin input
Non-maskable interrupt request signal (INTWDT2) generation
Reset signal generation by RESET pin input, low-voltage
detector, clock monitor, or watchdog timer (WDT2) overflow
WAIT pin input
Corresponding V850ES/JG3-H and V850ES/JH3-H Functions
HLDRQ pin input
CHAPTER 32 ON-CHIP DEBUG FUNCTION
−
Page 1391 of 1509