UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 730

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(4) UARTCn option control register 0 (UCnOPT0)
Caution Do not set the UCnSRT and UCnSTT bits (to 1) during SBF reception (UCnSRF bit = 1).
The UCnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTCn register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
(n = 0 to 4)
UCnOPT0
After reset: 14H
• SBF (Sync Brake Field) reception is judged during LIN communication.
• The UCnSRF bit is held at 1 when an SBF reception error occurs, and then SBF
• The UCnSRF bit is a read-only bit.
• This is the SBF reception trigger bit during LIN communication, and when read,
• Set the UCnSRT bit after setting the UCnPWR bit = UCnRXE bit = 1.
• This is the SBF transmission trigger bit during LIN communication, and when read,
• Set the UCnSTT bit after setting the UCnPWR bit = UCnTXE bit = 1.
UCnSRF
UCnSRT
UCnSRF
UCnSTT
reception is started again.
“0” is always read. For SBF reception, set the UCnSRT bit (to 1) to enable SBF
reception.
“0” is always read.
<7>
0
1
0
1
0
1
When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnRXE bit = 0 are set, or
upon normal end of SBF reception.
During SBF reception
SBF reception trigger
SBF transmission trigger
UCnSRT UCnSTT UCnSLS2 UCnSLS1 UCnSLS0 UCnTDL UCnRDL
R/W
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
6
Address: UC0OPT0 FFFFFA03H, UC1OPT0 FFFFFA13H,
5
UC2OPT0 FFFFFA23H, UC3OPT0 FFFFFA33H,
UC4OPT0 FFFFFA43H
SBF transmission trigger
4
SBF reception trigger
SBF reception flag
−
−
3
2
1
0
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