UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 492

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
TT0IOC2
(d) TMT0 I/O control register 2 (TT0IOC2)
(e) TMT0 counter read buffer register (TT0CNT)
(f) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1)
Note Set the valid edge selection of the unused alternate external input signals to “No edge detection”.
The value of the 16-bit counter can be read by reading the TT0CNT register.
If D
waveform are as follows.
Remark
Cycle = (D
Active level width = D
0
0
is set to the TT0CCR0 register and D
Figure 9-23. Setting of Registers in External Trigger Pulse Output Mode (2/2)
TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control
register 3 (TT0IOC3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1 (TT0OPT1),
and TMT0 counter write register (TT0TCW) are not used in the external trigger pulse output
mode.
0
0
+ 1) × Count clock cycle
0
1
× Count clock cycle
0
TT0EES1 TT0EES0
1
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
0
to the TT0CCR1 register, the cycle and active level of the PWM
0
TT0ETS1 TT0ETS0
0/1
0/1
Select valid edge of external
trigger input (EVTT0 pin)
Page 492 of 1509
Note