UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 446

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(5) TMT0 I/O control register 1 (TT0IOC1)
The TT0IOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals (TIT00,
TIT01 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TT0IOC1
After reset: 00H
Cautions 1. Rewrite the TT0IS3 to TT0IS0 bits when the TT0CTL0.TT0CE bit = 0.
TT0IS3
TT0IS1
0
0
1
1
0
0
1
1
7
0
R/W
2. The TT0IS3 and TT0IS2 bits are valid only in the free-running timer
TT0IS2
TT0IS0
6
0
0
1
0
1
0
1
0
1
(The same value can be written when the TT0CE bit = 1.) If rewriting
was mistakenly performed, clear the TT0CE bit to 0 and then set the
bits again.
mode (only when the TT0OPT0.TT0CCS1 bit = 1) and the pulse width
measurement mode. In all other modes, a capture operation is not
performed.
The TT0IS1 and TT0IS0 bits are valid only in the free-running timer
mode (only when the TT0OPT0. TT0CCS0 bit = 1) and the pulse width
measurement mode. In all other modes, a capture operation is not
performed.
Address: FFFFF604H
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Capture trigger input signal (TIT01 pin) valid edge setting
Capture trigger input signal (TIT00 pin) valid edge setting
5
0
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
4
0
TT0IS3
3
TT0IS2
2
TT0IS1
1
TT0IS0
0
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