UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 255

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(b) Notes on rewriting the TAAnCCR0 register
To change the value of the TAAnCCR0 register to a smaller value, stop counting once and then change the set
value.
If the value of the TAAnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
If the value of the TAAnCCR0 register is changed from D
less than D
been rewritten. Consequently, the value that is compared with the 16-bit counter is D
Because the count value has already exceeded D
and then counts up again from 0000H. When the count value matches D
generated.
Therefore, the INTTAAnCC0 signal may not be generated at the valid edge count of “(D
times” as originally expected, but may be generated at the valid edge count of “(10000H + D
Remark
INTTAAnCC0 signal
TAAnCCR0 register
1
n = 0 to 3, 5
, the count value is transferred to the CCR0 buffer register as soon as the TAAnCCR0 register has
16-bit counter
TAAnCE bit
FFFFH
0000H
External event
count signal
interval (1)
(D
1
+ 1)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
D
1
D
1
2
, however, the 16-bit counter counts up to FFFFH, overflows,
External event count signal
interval (NG)
(10000H + D
D
2
D
1
1
to D
2
+ 1)
2
while the count value is greater than D
D
2
D
2
External event
count signal
interval (2)
(D
D
2
2
+ 1)
2
, the INTTAAnCC0 signal is
2
.
1
+ 1) times” or “(D
2
+ 1) times”.
Page 255 of 1509
2
2
+ 1)
but