UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1317

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
25.5.2 Releasing IDLE2 mode
external interrupt request signal (INTP0 to INTP18 pin input), unmasked internal interrupt request signal from the
peripheral functions operable in the IDLE2 mode, or reset signal (reset by RESET pin input, WDT2RES signal, low-voltage
detector (LVI), or clock monitor (CLM)). The PLL returns to the operating status it was in before the IDLE2 mode was set.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal), unmasked
After the IDLE2 mode has been released, the normal operation mode is restored.
(1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request
(2) Releasing IDLE2 mode by reset
Non-maskable interrupt request
signal
Maskable interrupt request signal
signal
The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is processed as follows.
The same operation as the normal reset operation is performed.
Caution The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is
Release Source
issued, the IDLE2 mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
issued (including a non-maskable interrupt request signal), the IDLE2 mode is released and that interrupt
request signal is acknowledged.
PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not released.
Table 25-6. Operation After Releasing IDLE2 Mode by Interrupt Request Signal
Execution branches to the handler address after securing the prescribed setup time.
Execution branches to the handler address
or the next instruction is executed after
securing the prescribed setup time.
Interrupt Enabled (EI) Status
CHAPTER 25 STANDBY FUNCTION
The next instruction is executed after
securing the prescribed setup time.
Interrupt Disabled (DI) Status
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