UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 951

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Remark The AL bit is valid only in the single-shot mode.
Remarks 1. The CCERC bit is used to clear the C0ERC and C0INFO registers for re-initialization or forced
Remarks 1. Detection of a valid receive message frame is not dependent upon the existence or non-
CCERC
VALID
0
1
AL
0
1
0
1
2. When the C0ERC and C0INFO registers have been cleared, the CCERC bit is also cleared to 0
3. The CCERC bit can be set to 1 at the same time as a request to change the initialization mode to
4. If the CCERC bit is set to 1 immediately after the INIT mode is entered in the self test mode, the
2. Clear the VALID bit (0) before changing the initialization mode to an operation mode.
3. If only two CAN nodes are connected to the CAN bus with one transmitting a message frame in
4. To clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the VALID bit is cleared.
The C0ERC and C0INFO registers are not cleared in the initialization mode.
The C0ERC and C0INFO registers are cleared in the initialization mode.
recovery from the bus-off status. This bit can be set to 1 only in the initialization mode.
automatically.
an operation mode is made.
receive data may be corrupted.
existence of the storage in the receive message buffer (data frame) or transmit message buffer
(remote frame).
the normal mode and the other in the receive-only mode, since no ACK is generated in the
receive-only mode, the VALID bit is not set to 1 before the transmitting node enters the error
passive status.
If it is not cleared, perform clearing processing again.
Re-transmission is not executed in case of an arbitration loss in the single-shot mode.
Re-transmission is executed in case of an arbitration loss in the single-shot mode.
A valid message frame has not been received since the VALID bit was last cleared to 0.
A valid message frame has been received since the VALID bit was last cleared to 0.
Bit to set operation in case of arbitration loss
Valid receive message frame detection bit
Error counter clear bit
CHAPTER 20 CAN CONTROLLER
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