UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 341

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(7) TABn option register 0 (TABnOPT0)
The TABnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TABnOPT0
(n = 0, 1)
After reset: 00H
Note The TAB1CMS bit is used for the motor control function. For details,
Cautions 1. Rewrite the TABnCCS3 to TABnCCS0 bits when the
Remark
TABnCCS3
TABnCCSm
Set (1)
Reset (0)
The TABnCCSm bit setting is valid only in the free-running timer mode.
• The TABnOVF bit is set to 1 when the 16-bit counter count value overflows from
• An interrupt request signal (INTTABnOV) is generated at the same time that the
• The TABnOVF bit is not cleared even when the TABnOVF bit or the TABnOPT0
• The TABnOVF bit can be both read and written, but the TABnOVF bit cannot be
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
TABnOVF bit is set to 1. The INTTABnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
register are read when the TABnOVF bit = 1.
set to 1 by software. Writing 1 has no effect on the operation of TABn.
0
1
7
TABnOVF
see CHAPTER 11 MOTOR CONTROL FUNCTION.
TABnCCS2 TABnCCS1 TABnCCS0
2. Be sure to set bit 3 to “0”.
Compare register selected
Capture register selected
m = 0 to 3
R/W
6
TABnCTL0.TABnCE bit = 0.
written when the TABnCE bit = 1.)
mistakenly performed, clear the TABnCE bit to 0 and then
set the bits again.
function is not used, be sure to also set bit 2 to “0”.
Address:
Overflow occurred
TABnOVF bit 0 written or TABnCTL0.TABnCE bit = 0
TABnCCRm register capture/compare selection
5
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
TAB0OPT0 FFFFF545H, TAB1OPT0 FFFFF565H
TABn overflow detection
4
3
0
(The same value can be
TAB1CMS
When the motor control
2
Note
TABnCUF TABnOVF
If rewriting was
1
0
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