UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 372

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOABnk pin. If the trigger
is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The output of the
TOABn0 pin is inverted. The TOABnk pin outputs a high level regardless of the status (high/low) when a trigger is
generated.)
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal (INTTABnCCk) is generated when the count value of the 16-bit counter matches the value
of the CCRk buffer register.
counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H.
as the trigger.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
TABn waits for a trigger when the TABnCE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal (INTTABnCC0) is generated when the 16-bit counter counts up next time after its
The value set to the TABnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
The valid edge of the external trigger input signal or setting the software trigger (TABnCTL1.TABnEST bit) to 1 is used
Remark
TABnCTL0
Active level width = (Set value of TABnCCRk register) × Count clock cycle
Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TABnCCRk register)/(Set value of TABnCCR0 register + 1)
(a) TABn control register 0 (TABnCTL0)
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark
k = 1 to 3,
m = 0 to 3,
n = 0, 1
TABnCE
0/1
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (1/3)
n = 0, 1
0
0
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
0
TABnCKS2 TABnCKS1 TABnCKS0
0/1
0/1
0/1
Select count clock
0: Stop counting
1: Enable counting
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