UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 405

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
detected, the count value of the 16-bit counter is stored in the TABnCCRm register, and a capture interrupt request signal
(INTTABnCCm) is generated.
generates an overflow interrupt request signal (INTTABnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TABnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction
by software.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TABnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIABnm pin is
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
Remark
m = 0 to 3,
n = 0, 1
INTTABnCC0 signal
INTTABnCC1 signal
INTTABnCC2 signal
INTTABnCC3 signal
TABnCCR0 register
TABnCCR1 register
TABnCCR2 register
TABnCCR3 register
INTTABnOV signal
TIABn0 pin input
TIABn1 pin input
TIABn2 pin input
TIABn3 pin input
Figure 8-30. Basic Timing in Free-Running Timer Mode (Capture Function)
16-bit counter
TABnOVF bit
TABnCE bit
FFFFH
0000H
0000
0000
0000
0000
D
20
D
00
D
30
D
10
CLR instruction
D
Cleared to 0 by
00
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
D
D
20
D
01
D
10
30
D
11
D
21
D
31
D
01
Cleared to 0 by
CLR instruction
D
11
D
12
D
D
21
D
02
31
D
22
D
32
D
D
CLR instruction
Cleared to 0 by
02
12
D
03
D
D
D
13
32
22
D
D
33
03
D
23
D
13
D
D
33
23
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