UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 295

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Operation timing in free-running timer mode
(a) Interval operation with TAAnCCRm register used as compare register
When 16-bit timer/event counter AA is used as an interval timer with the TAAnCCRm register used as a
compare register, software processing is necessary for setting a comparison value to generate the next
interrupt request signal each time the INTTAAnCCm signal has been detected.
When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TAAnCCRm register must be re-set in the
interrupt servicing that is executed when the INTTAAnCCm signal is detected.
The set value for re-setting the TAAnCCRm register can be calculated by the following expression, where “D
is the interval period.
Remark
Compare register default value: D
Value set to compare register second and subsequent times: Previous set value + D
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
INTTAAnCC1 signal
INTTAAnCC0 signal
TAAnCCR1 register
TAAnCCR0 register
TOAAn1 pin output
TOAAn0 pin output
16-bit counter
m = 0, 1
n = 0 to 3, 5
TAAnCE bit
FFFFH
0000H
Interval period
Interval period
D
(D
(D
m
00
00
D
10
+ 1)
− 1
D
10
+ 1)
D
00
10
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Interval period
(10000H +
D
01
Interval period
− D
(10000H +
D
D
D
00
11
)
01
01
− D
D
Interval period
10
D
11
)
(D
11
02
− D
D
Interval period
02
01
D
(10000H +
)
D
02
12
Interval period
− D
(10000H +
D
D
D
11
03
12
)
12
− D
D
03
02
D
)
Interval period
03
(10000H +
D
Interval period
13
(10000H +
D
− D
04
D
− D
D
12
13
)
D
13
03
04
)
m
D
04
D
D
14
05
Page 295 of 1509
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