UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 753

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
17.7 Dedicated Baud Rate Generator
generates a serial clock during transmission and reception with UARTCn. Regarding the serial clock, a dedicated baud
rate generator output can be selected for each channel.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
(a) Base clock
(b) Serial clock generation
Note Only UARTC0 is valid; setting UARTC1 and UARTC4 is prohibited.
Remarks 1. n = 0 to 4
When the UCnCTL0.UCnPWR bit is 1, the clock selected by the UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0
bits is supplied to the 8-bit counter. This clock is called the base clock (f
A serial clock can be generated by setting the UCnCTL1 register and the UCnCTL2 register (n = 0 to 4).
The base clock is selected by UCnCTL1.UCnCKS3 to UCnCTL1.UCnCKS0 bits.
The frequency division value for the 8-bit counter can be set using the UCnCTL2.UCnBRS7 to
UCnCTL2.UCnBRS0 bits.
ASCKC0
f
f
XX
XX
2. f
f
f
f
XX
XX
XX
f
f
f
/1024
/2048
XX
XX
XX
f
f
f
/128
/256
/512
XX
XX
XX
/16
/32
/64
Note
f
XX
UCLK
/2
/4
/8
:
UCnCKS3 to UCnCKS0
: Base clock frequency
Main clock frequency
Figure 17-19. Configuration of Baud Rate Generator
UCnCTL1:
UCnPWR
Selector
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
f
UCLK
UCnPWR, UCnTXEn
UCnBRS7 to UCnBRS0
(or UCnRXE bit)
Match detector
8-bit counter
UCnCTL2:
bits
UCLK
1/2
).
Baud rate
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