UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1164

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UPD70F3771GF-GAT-AX

Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet

Specifications of UPD70F3771GF-GAT-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(14) UF0 configuration/interface/endpoint descriptor registers 0 to 255 (UF0CIE0 to UF0CIE255)
(n = 0 to 255)
Cautions 1. To rewrite these registers, set the EP0NKA bit to 1 before reading the register contents, and
UF0CIEn
These registers store the value to be returned in response to the GET_DESCRIPTOR Configuration request.
These registers can be read or written in 8-bit units. However, data can be written to these registers only when
the EP0NKA bit is set to 1.
Descriptor information of up to 256 bytes can be stored in these registers. Store each descriptor in the order of
Configuration, Interface, and Endpoint (see Table 21-6). If there are two or more Interfaces, repeatedly store the
data following the Interface descriptor.
The range of the valid data that can be set to these registers varies according to the setting of the UF0DSCL
register. In addition to the descriptors listed in Table 21-7, descriptors peculiar to classes and vendors can also be
stored.
If all the values are fixed, they can be stored in ROM.
2. Use the value defined by USB Specification Ver. 2.0 and the latest Class Specification as the
7
rewrite the register contents after confirming that the bit has been set, in order to prevent
conflict between a read access and a write access.
set value.
002001C6H
002001D8H
002001EAH
002001F8H
00200206H
002002xxH
002002xxH+9
002002xxH+16
002002xxH+23
6
Address
:
:
Table 21-6. Mapping of UF0CIEn Register
5
Configuration descriptor (9 bytes)
Interface descriptor (9 bytes)
Endpoint1 descriptor (7 bytes)
Endpoint2 descriptor (7 bytes)
Endpoint3 descriptor (7 bytes)
Interface descriptor (9 bytes)
Endpoint1 descriptor (7 bytes)
Endpoint2 descriptor (7 bytes)
Endpoint3 descriptor (7 bytes)
4
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
Descriptor Stored
2
:
:
1
0
002001C6H to
002003C4H
Address
Page 1164 of 1509
Undefined
After reset

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