UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1092

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Bit position
3
2
1
0
DMAED
SETRQ
CLRRQ
EPHALT
Bit name
This bit indicates that the DMA end (TC) signal for Endpoint n (n = 1 to 4, 7) is active.
When this bit is set to 1, the DMA request signal for Endpoint n becomes inactive. The
DMA request signal for Endpoint n does not become active unless FW enables DMA
transfer.
Use the UF0DMS0 register to confirm on which endpoint the operation is actually
performed. However, this bit is not automatically cleared to 0 even if the UF0DMS0
register is read by FW.
This bit indicates that the SET_XXXX request to be automatically processed has been
received and automatically processed (XXXX = CONFIGURATION or FEATURE).
This bit is set to 1 after completion of the status stage. Reference the UF0SET register to
identify what is the target of the request. This bit is not automatically cleared to 0 even if
the UF0SET register is read by FW.
The EPHALT bit is also set to 1 when the SET_FEATURE Endpoint request has been
received.
This bit indicates that the CLEAR_FEATURE request has been received and
automatically processed.
This bit is set to 1 after completion of the status stage. Reference the UF0CLR register to
identify what is the target of the request. This bit is not automatically cleared to 0 even if
the UF0CLR register is read by FW.
This bit indicates that an endpoint has stalled.
This bit is also set to 1 when an endpoint has stalled by setting FW.
Identify the endpoint that has stalled, by referencing the UF0EPS2 register. This bit is not
automatically cleared to 0 even when the CLEAR_FEATURE Endpoint,
SET_INTERFACE, or SET_CONFIGURATION request is received. It is not automatically
cleared to 0, either, if the next SETUP token is received in case of overrun of Endpoint0.
Caution Even if Halt Feature of Endpoint0 is set and this interrupt request is
1: DMA end signal for Endpoint n has been input (interrupt request is generated).
0: DMA end signal for Endpoint n has not been input (default value).
1: SET_XXXX request to be automatically processed has been received (interrupt
0: SET_XXXX request to be automatically processed has not been received (default
1: CLEAR_FEATURE request has been received (interrupt request is generated).
0: CLEAR_FEATURE request has not been received (default value).
1: Endpoint has stalled (interrupt request is generated).
0: Endpoint has not stalled (default value).
request is generated).
value).
generated, bit 0 of the UF0EPS2 register is masked and cleared to 0
between when a SET_FEATURE Endpoint0, CLEAR_FEATURE Endpoint0,
or GET_STATUS Endpoint0 request, or FW-processed request is received
and when a SETUP token other than the above is received.
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
Function
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