UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1437

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
V850ES/JG3-H, V850ES/JH3-H
(T
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
SCL0n clock frequency
Bus free time
(Between start and stop conditions)
Hold time
SCL0n clock low-level width
SCL0n clock high-level width
Setup time for start/restart conditions
Data hold
time
Data setup time
SDA0n and SCL0n signal rise time
SDA0n and SCL0n signal fall time
Stop condition setup time
Pulse width of spike suppressed by
input filter
Capacitive load of each bus line
Notes 1. When the start condition is satisfied, the first clock pulse is generated after the hold time.
A
(6) I
= −40 to +85°C, V
2. The system requires a minimum of 300 ns hold time internally for the SDA0n signal (at V
3. If the system does not extend the SCL0n signal low hold time (t
4. The high-speed mode I
5. Cb: Total capacitance of one bus line (unit: pF)
2
C bus mode
Note 1
•
•
n = 0 to 2
CBUS compatible master
I
signal) in order to occupy the undefined area at the falling edge of SCL0n.
needs to be satisfied.
mode I
2
C mode
Parameter
If the system does not extend the SCL0n signal low hold time:
t
If the system extends the SCL0n signal low hold time:
Output the next data bit to the SDA0n line before the SCL0n line is released (t
SU:DAT
1,250 ns: Normal mode I
2
C bus so that it meets the following conditions.
≥ 250 ns
DD
= EV
DD
= UV
2
C bus can be used in a normal-mode I
f
t
t
t
t
t
t
t
t
t
t
t
Cb
CLK
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
SP
DD
= AV
Symbol
2
C bus specification).
<69>
<70>
<71>
<72>
<73>
<74>
<75>
<76>
<77>
<78>
<79>
REF0
= AV
REF1
0
MIN.
250
4.7
4.0
4.7
4.0
4.7
5.0
Note 2
4.0
0
−
−
−
−
, V
Normal Mode
SS
= AV
CHAPTER 33 ELECTRICAL SPECIFICATIONS
SS
MAX.
1000
100
300
400
= 0 V)
−
−
−
−
−
−
−
−
−
−
2
LOW
C bus system. In this case, set the high-speed
), only the maximum data hold time (t
20 + 0.1Cb
20 + 0.1Cb
100
0
MIN.
1.3
0.6
1.3
0.6
0.6
Note 2
0.6
High-Speed Mode
0
−
0
−
Note 4
Note 5
Note 5
Rmax.
+ t
0.9
MAX.
400
300
300
400
50
SU:DAT
−
−
−
−
−
−
−
−
Note 3
IHmin.
Page 1437 of 1509
= 1,000 + 250 =
of the SCL0n
kHz
μ
μ
μ
μ
μ
μ
μ
ns
ns
ns
μ
ns
pF
s
s
s
s
s
s
s
s
Unit
HD
:
DAT
)