UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 879

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
19.16.2 Master operation in multimaster system
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Remark
Note Confirm that the bus release status (IICCLn.CLDn bit = 1, IICCLn.DADn bit = 1) has been maintained for a
communicating product.
certain period (1 frame, for example). When the SDA0n pin is constantly low level, determine whether to
release the I
1
No
n = 0 to 2, m = 0, 1
ACKEn = WTIMn = SPIEn = 1
Set STCENn, IICRSVn
Confirm bus status
reservation enable
INTIICn interrupt
Master operation
OCKSm ← XXH
Communication
IICCLn ← XXH
SVAn ← XXH
IICCn ← XXH
IICRSVn = 0?
IICXn ← 0XH
IICFn ← 0XH
SPDn = 1?
occurred?
SPIEn = 1
IICEn = 1
Set ports
started?
START
A
2
Yes
Yes
Yes
C0n bus (SCL0n, SDA0n pins = high level) by referring to the specifications of the
Yes
(communication start
request issued)
• Waiting for slave specification from another master
• Waiting for communication start request (depending on user program)
Confirmation of bus
status is in progress
Figure 19-19. Master Operation in Multimaster System (1/3)
Note
reservation disable
Communication
(no communication start request)
No
Bus release status for a certain period
No
No
Refer to Table 4-20 Settings When Port Pins Are Used for Alternate Functions
to set the I
Transfer clock selection
Local address setting
Start condition setting
Slave operation
B
2
C mode before this function is used.
STCENn = 1?
INTIICn interrupt
Yes
Slave operation
SPIEn = 0
occurred?
Yes
No
No
Waiting for communication request
INTIICn interrupt
SPDn = 1?
SPTn = 1
occurred?
Yes
Yes
No
No
CHAPTER 19 I
Communication start preparation
(stop condition generation)
Waiting for stop condition
detection
Slave operation
Page 879 of 1509
2
C BUS