UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 271

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOAAn1 pin. After
the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is
generated again while the one-shot pulse is being output, it is ignored.
value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTAAnCC1 is
generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
trigger.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TAAnCE bit is set to 1, 16-bit timer/event counter AA waits for a trigger. When the trigger is generated, the
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTAAnCC0 is generated when the 16-bit counter counts after its count
The valid edge of an external trigger input or setting the software trigger (TAAnCTL1.TAAnEST bit) to 1 is used as the
Remark
External trigger input
Output delay period = (Set value of TAAnCCR1 register) × Count clock cycle
Active level width = (Set value of TAAnCCR0 register − Set value of TAAnCCR1 register + 1) × Count clock cycle
INTTAAnCC0 signal
INTTAAnCC1 signal
(only when software
TAAnCCR0 register
TAAnCCR1 register
TOAAn0 pin output
TOAAn1 pin output
(TIAAn0 pin input)
trigger is used)
16-bit counter
n = 0 to 3, 5
TAAnCE bit
FFFFH
0000H
Figure 7-26. Basic Timing in One-Shot Pulse Output Mode
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
D
D
0
0
0
1
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)
Page 271 of 1509