UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1301

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(7) Noise elimination control register (INTNFC)
Remarks 1. Since sampling is performed 3 times, the reliably eliminated noise width is 2 sampling clocks.
Analog noise elimination and digital noise elimination can be selected for the INTP02 pin. The noise elimination
settings are performed using the INTNFC register.
When analog noise elimination is selected, the input level of the pin is detected as an edge by maintaining it for a
specific time or longer.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among
f
Even when digital noise elimination is selected, using f
interrupt request signal to release the IDLE1, IDLE2, and STOP modes.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution After the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital
XX
/64, f
2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is
XX
INTNFC
/128, f
generated if noise synchronized with the sampling clock is input.
noise eliminator. Therefore, if an INTP02 valid edge is input within these 3 sampling clocks after
the sampling clock has been changed, an interrupt request signal may be generated. Therefore,
be careful about the following points when using the interrupt and DMA functions.
• When using the interrupt function, after the 3 sampling clocks have elapsed, enable interrupts
• When using the DMA function (started by INTP02), enable DMA after 3 sampling clocks have
After reset: 00H
after the interrupt request flag (PIC2.PIF2 bit) has been cleared.
elapsed.
XX
/256, f
INTNFEN
INTNFEN
INTNFC2
0
1
0
0
0
0
1
1
XX
Other than above
/512, f
Analog noise elimination (60 ns (TYP.))
Digital noise elimination
INTNFC1
R/W
0
0
0
1
1
0
0
XX
/1,024, and f
CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Address: FFFFF728H
INTNFC0
0
0
1
0
1
0
1
Settings of INTP02 pin noise elimination
XT
f
f
f
f
f
f
Setting prohibited
XX
XX
XX
XX
XX
XT
. Sampling is performed 3 times.
/64
/128
/256
/512
/1,024
(subclock)
0
XT
as the sampling clock makes it possible to use the INTP02
0
Digital sampling clock
INTNFC2 INTNFC1 INTNFC0
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