UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 374

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(d) TABn I/O control register 2 (TABnIOC2)
(e) TABn counter read buffer register (TABnCNT)
(f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
TABnIOC2
The value of the 16-bit counter can be read by reading the TABnCNT register.
If D
Cycle = (D
TOABn1 pin PWM waveform active level width = D
TOABn2 pin PWM waveform active level width = D
TOABn3 pin PWM waveform active level width = D
and D
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are
0
is set to the TABnCCR0 register, D
3
to the TABnCCR3 register, the cycle and active level of the PWM waveform are as follows.
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (3/3)
0
2. Updating TABn capture/compare register 2 (TABnCCR2) and TABn capture/compare
3. n = 0, 1
+ 1) × Count clock cycle
0
not used in the external trigger pulse output mode.
register 3 (TABnCCR3) is enabled by writing TABn capture/compare register 1
(TABnCCR1).
0
0
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
1
to the TABnCCR1 register, D
TABnEES1
0/1
1
2
3
× Count clock cycle
× Count clock cycle
× Count clock cycle
TABnEES0
0/1
TABnETS1 TABnETS0
0/1
2
to the TABnCCR2 register,
0/1
Select valid edge of
external trigger input
Select valid edge of
external event count input
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