UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 888

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Notes 1. Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn.
Remark
2. To cancel the slave wait state, write FFH to IICn or set WRELn.
WRELn
INTIICn
WRELn
INTIICn
ACKDn
MSTSn
ACKDn
MSTSn
ACKEn
ACKEn
Processing by master device
WTIMn
SDA0n
WTIMn
Transfer lines
SCL0n
n = 0 to 2
Processing by slave device
SPDn
TRCn
SPDn
TRCn
STDn
SPTn
STDn
SPTn
STTn
STTn
IICn
IICn
H
H
L
H
H
L
L
L
L
Transmit
Receive
(When 9-Clock Wait Is Selected for Both Master and Slave) (3/3)
IICn ← FFH Note2
IICn ← data Note 1
Figure 19-23. Example of Master to Slave Communication
D7
Note 2
1
D6
2
D5
3
D4
4
D3
5
(c) Stop condition
D2
6
D1
7
D0
8
ACK
9
IICn ← FFH Note2
Note 2
condition
Stop
(when SPIEn = 1)
(when SPIEn = 1)
condition
Start
CHAPTER 19 I
IICn ← address
AD6
1
AD5
2
Page 888 of 1509
2
C BUS