UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 202

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Main clock oscillator
(2) Subclock oscillator
(3) Main clock oscillator stop control
(4) Internal oscillator
(5) Prescaler 1
(6) Prescaler 2
(7) Prescaler 3
(8) PLL
The main clock oscillator oscillates the following frequencies (f
• In clock-through mode
• In PLL mode
The sub-resonator oscillates a frequency of 32.768 kHz (f
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when
the PCC.CLS bit = 1).
Oscillates a frequency (f
This prescaler generates the clock (f
TAA, TAB, TMM, TMT, CSIF, UARTC, I
This circuit divides the main clock (f
The clock generated by prescaler 2 (f
and internal system clock (f
f
This circuit divides the clock generated by the main clock oscillator (f
supplies that clock to the real-time counter (RTC) block.
This circuit multiplies the clock generated by the main clock oscillator (f
It operates in two modes: clock-through mode in which f
is output. These modes can be selected by using the PLLCTL.SELPLL bit.
CLK
f
f
X
X
is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin.
= 3.0 to 6.0 MHz
= 3.0 to 6.0 MHz (×8)
R
) of 220 kHz (TYP.).
CLK
).
XX
).
XX
XX
2
C, CAN, ADC, DAC, WDT2
to f
to f
XX
XX
/1,024) to be supplied to the following on-chip peripheral functions:
/32) is supplied to the selector that generates the CPU clock (f
X
XT
CHAPTER 6 CLOCK GENERATION FUNCTION
is output as is, and PLL mode in which a multiplied clock
).
X
).
X
X
) to a specific frequency (32.768 kHz) and
) by 8.
Page 202 of 1509
CPU
)