UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 288

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UPD70F3771GF-GAT-AX

Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet

Specifications of UPD70F3771GF-GAT-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-H, V850ES/JH3-H
detected, the count value of the 16-bit counter is stored in the TAAnCCRm register, and a capture interrupt request signal
(INTTAAnCCm) is generated.
generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues counting.
At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR
instruction by software.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TAAnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIAAnm pin is
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
Remark
INTTAAnCC1 signal
INTTAAnCC0 signal
TAAnCCR1 register
TAAnCCR0 register
INTTAAnOV signal
TIAAn0 pin input
TIAAn1 pin input
16-bit counter
TAAnOVF bit
Figure 7-35. Basic Timing in Free-Running Timer Mode (Capture Function)
TAAnCE bit
n = 0 to 3, 5
FFFFH
0000H
D
00
D
CLR instruction
Cleared to 0 by
10
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
D
00
D
D
01
10
D
11
CLR instruction
Cleared to 0 by
D
D
01
02
D
11
D
12
CLR instruction
Cleared to 0 by
D
02
D
03
D
12
D
13
D
03
D
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