LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 10

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Board Timing Guidelines for the DDR SDRAM Controller IP Core
PCB Layout Recommendations for BGA Packages
SPI Serial Flash Programming Using ispJTAG on LatticeECP/EC FPGAs
Section III. LatticeECP/EC Family Handbook Revision History
Conclusion ..................................................................................................................................................... 18-15
Technical Support Assistance........................................................................................................................ 18-16
Introduction ...................................................................................................................................................... 19-1
Read Operation................................................................................................................................................ 19-2
Write Operation ................................................................................................................................................ 19-4
Address and Command Signals....................................................................................................................... 19-5
Board Design Guidelines ................................................................................................................................. 19-7
Technical Support Assistance.......................................................................................................................... 19-8
Appendix A. Example Extractions of Delays from Timing Reports .................................................................. 19-9
Introduction ...................................................................................................................................................... 20-1
Advantages and Disadvantages of BGA Packaging ........................................................................................ 20-1
PCB Layout ...................................................................................................................................................... 20-2
Plated Through Hole (Via) Placement.............................................................................................................. 20-2
BGA Board Layout Recommendations ............................................................................................................ 20-3
BGA Package Types........................................................................................................................................ 20-3
Further Information........................................................................................................................................... 20-3
Technical Support Assistance.......................................................................................................................... 20-3
Revision History ............................................................................................................................................... 20-3
Introduction ...................................................................................................................................................... 21-1
Related Documents.......................................................................................................................................... 21-1
Hardware and Software Requirements ............................................................................................................ 21-1
SPI/SPIX Differences ....................................................................................................................................... 21-1
Hardware.......................................................................................................................................................... 21-2
Software ........................................................................................................................................................... 21-6
Including the SPI Interface in the FPGA Design ............................................................................................ 21-14
Locking the Pins............................................................................................................................................. 21-16
Design Notes.................................................................................................................................................. 21-18
Conclusion ..................................................................................................................................................... 21-19
Technical Support Assistance........................................................................................................................ 21-19
Revision History ............................................................................................................................................... 22-1
Set-up Time Calculation for the Data Input (Max. Case) ........................................................................ 19-3
Hold Time Calculation for the Data Input (Min. Case)............................................................................. 19-3
Write Set-up ............................................................................................................................................ 19-4
Write Hold ............................................................................................................................................... 19-5
Set-up Calculation................................................................................................................................... 19-6
Hold Calculation ...................................................................................................................................... 19-7
SPI Serial Flash Sizing............................................................................................................................ 21-2
SPI Serial Flash Interface ....................................................................................................................... 21-3
ispJTAG Interface ................................................................................................................................... 21-3
Schematic ............................................................................................................................................... 21-5
Programming Procedure ......................................................................................................................... 21-7
Sample Code ........................................................................................................................................ 21-14
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LatticeECP/EC Family Data Sheet
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