LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 427
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Therefore:
Assumptions for write set-up and hold equations:
Therefore:
Write Hold
Therefore:
Assumptions for write set-up and hold equations:
Therefore:
Address and Command Signals
Address (ddr_ad) and command signals (ddr_cas, ddr_ras, ddr_we) should meet set-up (t
timings at DDR interface with respect to positive edge of ddr_clk. Address and command signals are clocked
using negative edge of pll_mclk inside the FPGA as shown below. The ddr_clk signal is a delayed by pad
delay and board delay at DDR interface compared to pll_mclk inside the FPGA. As a result, 1/2clkx of set-up
and hold is provided by design.
Clock Delay - Data Delay > 0
t
1. t
2. t
1/2 clk2x - t
3.75/2 - 0.75 > 0
1.125 > 0
Data Delay = t
Clock Delay = t
Data Delay - Clock Delay > 0
t
1. t
2. t
1/2 clk2x - t
3.75/2 - 0.75 > 0
1.125 > 0
CDQS
CDQS
BDDS
CDQ
BDDS
CDQ
+ 1/2 clk2x - t
+ 1/2 clk2x - t
and t
and t
and t
and t
CDQS
CDQS
BDD
DS
BDD
DH
CDQ
CDQS
> 0
> 0
are equal (board delays are same both for dqs_out and ddr_dq_out).
are equal (board delays are same both for dqs_out and ddr_dq_out).
are equal (both are output delays from I/O flop).
are equal (both are output delays from I/O flop).
+ t
+ 1/2 clk2x + t
DS
BDD
DH
+ t
+ t
BDDS
BDDS
- t
- t
CDQ
CDQ
DH
- t
- t
+ t
BDD
BDD
BDDS
> 0
> 0
18-5
for the DDR SDRAM Controller IP Core
Board Timing Guidelines
DS
) and hold (t
DH
)
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