LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 359
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Lattice ispTRACY Usage Guide
Figure 14-9. ispLA Project Setup Window - Trigger Setup options
The options available in the Trigger setup window are based on selected ispTRACY core options. In the Trace
Mode box, One Shot mode will always be available, but Sample After Trigger availability is dependent on selecting
Sample_After_Trigger Mode Logic => ON. The position slider can be used to select the trigger point anywhere
within the data memory depth. There are three preconfigured trigger positions in the drop-down menu box. They
are Pre-Trigger (5% before and 95% after trigger), Center (50% before and 50% after trigger) and Post Trigger
(95% before and 5% after trigger). In the Compare Mode box the options are also dependant on core configuration.
EV0 and EV1 are always available. The comparisons available and number of samples will be determined by the
Size Comparison Logic and Event Counter Size. The equal to comparison is always available. Additions compari-
sons include >, <. !=, <=, >=. The Trigger Condition box configures which event or combination of events will cause
the ispLA program to trigger and upload captured data from the device. In a simple case, this would be set to Wait
for EV0. More complex cases could possible be wait for EV0 and EV1, or after EV1 wait until EV0. The final two
boxed on this screen control the signal polarity of Trigger In (if available) and Trigger Out.
14-7
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