LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 404

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
and
then the REGISTER_FILE and STATE_MACHINE will be grouped in the FPGA inside a default boundary box. Now
assume that the REGISTER_FILE is mapped into PFU_4 and PFU_5 and the STATE_MACHINE is mapped into
PFU_3. The resulting preference generated by map in the
Notice the TOP/ hierarchy is not appended to the PGROUP identifier CRITICAL_GROUP. Also notice that
UGROUP attributes result in PGROUP preferences. There is no UGROUP preference.
If PGROUP attributes instead of UGROUP attributes had been used for Figure 16-4:
and
then the resulting preference generated by map in the .prf file would be:
So, with PGROUP attributes, the STATE_MACHINE module would be grouped together in one bounding box and
REGISTER_FILE module would be grouped together separately in another bounding box and the critical path
shown in Figure 16-4 will not be optimized.
These examples do not utilize all the possible tools available for floorplanning. Please refer to ispLEVER On-line
Help PGROUP section for many small syntax examples.
Floorplanner GUI Usage
Generally, the PGROUPs and UGROUPs are preferable to the Floorplanner GUI since they are easier to imple-
ment. For example, it is easier to type in a PGROUP attribute in the HDL code then to load the GUI with large
netlists and find the desired block and perform add the PGROUP via mouse clicks. More importantly, the GUI does
not allow the retention of floorplanning the way PGROUPing and UGROUPing does. Since the GUI does not back
annotate the grouping attributes into the HDL, the GUI operations have to be redone every time there is a new
design iteration.
The Floorplanner GUI can be useful for
• Viewing elements in a graphical environment to see a design’s logical hierarchy.
• Viewing existing PGROUPs and UGROUPs.
• Resizing regions and boundary boxes (BBOXes).
• Graphically placing regions, PGROUPs, and UGROUPs and then running map, place, route, and trace to
module REGISTER_FILE (<port_list>) /*synthesis ugroup=”CRITICAL_GROUP” */;
module STATE_MACHINE (<port_list>) /*synthesis ugroup=”CRITICAL_GROUP” */;
PGROUP “CRITICAL_GROUP”
module REGISTER_FILE (<port_list>) /*synthesis pgroup=”CRITICAL_GROUP” */;
module STATE_MACHINE (<port_list>) /*synthesis pgroup=”CRITICAL_GROUP” */;
PGROUP “TOP/CONTROLLER/STATE_MACHINE/CRITICAL_GROUP”
PGROUP “TOP/REGISTER_FILE/CRITICAL_GROUP”
see the effects. This is usually an iterative process before finding an optimal solution.
COMP “PFU_3”
COMP “PFU_4”
COMP “PFU_5”;
COMP “PFU_3”
COMP “PFU_4”
COMP “PFU_5”;
16-6
Lattice Semiconductor Design Floorplanning
.prf
file will be: