LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 306
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LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 306 of 478
- Download datasheet (13Mb)
Lattice Semiconductor
DCS MODE = NEG
At the falling edge (NEG) of SEL, the DCSOUT changes from CLK0 to CLK1.
DCS MODE = HIGH_LOW
SEL is active high (HIGH) to select CLK1, and the disabled output is LOW.
DCS MODE = LOW_LOW
SEL is active low (LOW) to select CLK0, and the disabled output is LOW.
DCS MODE = HIGH_HIGH
SEL is active high (HIGH) to select CLK1, and the disabled output is HIGH.
DCS MODE = LOW_HIGH
SEL is active low (LOW) to select CLK0, and the disabled output is HIGH.
DCSOUT
SEL
CLK1
DCSOUT
CLK1
SEL
CLK0
- Switch low at CLK1 falling edge.
- If SEL is low, output stays low at on
CLK1 rising edge. SEL must not
change during setup prior to rising clock.
DCS MODE = HIGH_LOW
SEL Falling edge:
- Wait for CLK1 falling edge,
- Switch output at CLK0 falling edge
latch output & remain low
DCS MODE = NEG
11-16
DCSOUT
sysCLOCK PLL Design and Usage Guide
SEL
CLK0
- Switch low at CLK0 falling edge.
- If SEL is high, output stays low at
on CLK0 rising edge.
SEL Rising edge:
- Wait for CLK0 falling edge,
- Switch output at CLK1 falling edge
DCS MODE = LOW_LOW
latch output & remain low
LatticeECP/EC and LatticeXP
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