LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 204
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-5. Example Generating Pseudo Dual Port RAM (RAM_DP) Using IPexpress
In the right-hand pane, options like Macro Type, Version, and Module_Name are device and selected module
dependent. These cannot be changed in IPexpress.
Users can change the directory where the generated module files will be placed by clicking the browse button in
the Project Path.
The File Name text box allows users to specify the entity and file name for the module they are about to generate.
Users must provide this name.
Design Entry, Verilog or VHDL, by default is the same as the project type. If the project is a VHDL project, the
selected Design Entry option will be “Schematic/ VHDL”, and “Schematic/ Verilog-HDL” if the project type is Verilog-
HDL.
Then click the Customize button. This opens another window where the RAM can be customized.
The the left-hand side of this window shows the block diagram of the module. The right-hand side includes the
Configuration tab.
9-5
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