LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 187
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LOCATE PGROUP “ vref_pg1” BANK 2;
LOCATE PGROUP “ vref_pg2” BANK 2;
The second example show V
V
which bank V
bank.
If the PGROUP VREF is not used, the software will automatically group all pins that need the same V
voltage. This preference is most useful when there is more than one bus using the same reference voltage and the
user wants to associate each of these buses to different V
Differential I/O Implementation
The LatticeECP/EC and LatticeXP devices support a variety of differential standards as detailed in the following
section.
LVDS
True LVDS (LVDS25) drivers are available on the left and right side of the devices. LVDS input support is provided
on all sides of the device. All four sides support LVDS using complementary LVCMOS drivers with external resis-
tors (LVDS25E).
Please refer to the LatticeECP/EC and LatticeXP data sheets for a more detailed explanation of these LVDS imple-
mentations.
BLVDS
All single-ended sysIO buffer pairs in the LatticeECP family support the Bus-LVDS standard using complementary
LVCMOS drivers with external resistors.
Please refer to the LatticeECP/EC and LatticeXP data sheets to learn more about BLVDS implementation.
RSDS
All single-ended sysIO buffers pairs in the LatticeECP family support the RSDS standard using complementary
LVCMOS drivers with external resistors. This mode uses LVDS25E with an alternative resistor pack.
Please refer to the LatticeECP/EC and LatticeXP data sheets for a detailed explanation of RSDS implementation.
LVPECL
All the sysIO buffers will support LVPECL inputs. LVPECL outputs are supported using a complementary LVCMOS
driver with external resistors.
Please refer to the LatticeECP/EC and LatticeXP data sheets for further information on LVPECL implementation.
Differential SSTL and HSTL
All single-ended sysIO buffers pairs in the LatticeECP family support differential SSTL and HSTL. Please refer to
the LatticeECP/EC and LatticeXP data sheets for a detailed explanation of Differential HSTL and SSTL implemen-
tation.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
REF
must then be locked to either V
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
REF
group should be located. The software will then assign these to either V
REF
groups, “vref_pg1” assigned to V
REF1
or V
REF2
using LOCATE preference. Or, the user can simply designate to
8-13
REF
resources.
REF
“ref1” and “vref_pg2” assigned to “ref2”.
LatticeECP/EC and LatticeXP
sysIO Usage Guide
REF1
or V
REF
REF2
reference
of the
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