LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 335

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Table 12-1. Configuration Pins for LatticeECP/EC Devices
Dedicated Control Pins
The following is a description of the LatticeECP/EC’s dedicated sysCONFIG pins used for controlling configuration.
CFG[0:2]
The Configuration Mode pins CFG[0:2] are input pins. They are used to select the configuration mode. Depending
on the configuration mode selected, different groups of dual-purpose configuration pins will be activated on Power-
On-Reset or when the PROGRAMN pin is driven low.
PROGRAMN
The PROGRAMN pin is an input to the device used to initiate a Programming sequence. A high to low signal
applied to the pin sets the device into configuration mode. The PROGRAMN pin can be used to trigger program-
ming other than at powering up. If the device is using JTAG, the device will ignore the PROGRAMN pin until the
device is released from the JTAG mode.
INITN
The INITN pin is a bidirectional open drain control pin. It is capable of driving a low pulse out as well as detecting a
low pulse driven in. When the PROGRAMN Pin is driven low, or after the internal Power-On-Reset signal is
released during Power-up, the INITN pin will be driven low to reset the configuration circuitry and any External
PROM. The configuration memory will be cleared and the INITN pin will remain low as long as the PROGRAMN pin
is low. To delay configuration the INITN pin can be held low externally. The device will not enter configuration mode
as long as the INITN pin is held low. Toggling the PROGRAMN pin in Serial and Parallel programming modes will
initiate the configuration sequence and reset the INITN pin. For SPI mode, power cycling the device will initiate the
reconfiguration sequence.
During configuration, the INITN pin becomes an error detection pin. It will be driven low whenever a configuration
error occurs.
DONE
The DONE pin is a bidirectional control pin. It can be configured as an open drain or active drive control pin. The
DONE pin will be driven low when the device is in configuration mode and the internal DONE bit is not pro-
grammed. When the INITN and PROGRAMN pins are high and the DONE bit is programmed, the DONE pin will be
CFG[0:2]
PROGRAMN
INITN
DONE
CCLK
DI/CSSPIN
DOUT/CSON
CSN
CS1N
WRITEN
BUSY/SISPI
D[0:7]/SPID[7:0]
TDI
TDO
TCK
TMS
1. Defaults to open drain with an internal pull-up.
Pin(s)
1
Input
Input
Bi-directional open drain
Bi-directional
Output or input
Input/output with weak pull-up
Output
Input
Input
Input
Output
Input or output
Input with pull-up
Output
Input with hysteresis, no pull-up
Input with pull-up
Description
Default Pin Function
12-2
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
LatticeECP/EC sysCONFIG Usage Guide
—
—
—
—
—
—
—
All
All
All
All
MASTER = output, SLAVE = input
SERIAL/PARALLEL
PARALLEL
PARALLEL
PARALLEL
PARALLEL/SPI
PARALLEL/SPI
JTAG
JTAG
JTAG
JTAG
SERIAL/SPI
Mode Used