LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 5

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Memory Usage Guide for LatticeECP/EC and LatticeXP Devices
LatticeECP/EC and LatticeXP DDR Usage Guide
Appendix A. HDL Attributes for Synplify
VHDL Synplify/Precision RTL Synthesis.......................................................................................................... 8-14
Verilog for Synplify ........................................................................................................................................... 8-17
Verilog for Precision RTL Synthesis................................................................................................................. 8-19
Appendix B. sysIO Attributes Using Preference Editor User Interface............................................................. 8-21
Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-22
Introduction ........................................................................................................................................................ 9-1
Memories in LatticeECP/EC and LatticeXP Devices ......................................................................................... 9-1
Utilizing IPexpress.............................................................................................................................................. 9-3
Memory Modules................................................................................................................................................ 9-7
Initializing Memory ........................................................................................................................................... 9-51
Technical Support Assistance.......................................................................................................................... 9-53
Revision History ............................................................................................................................................... 9-53
Appendix A. Attribute Definitions...................................................................................................................... 9-54
Introduction ...................................................................................................................................................... 10-1
DDR SDRAM Interfaces Overview................................................................................................................... 10-1
Implementing DDR Memory Interfaces with the LatticeECP/EC Devices........................................................ 10-2
Syntax ..................................................................................................................................................... 8-14
Examples ................................................................................................................................................ 8-14
Syntax ..................................................................................................................................................... 8-17
Examples ................................................................................................................................................ 8-17
Syntax ..................................................................................................................................................... 8-19
Example .................................................................................................................................................. 8-19
IOBUF ..................................................................................................................................................... 8-22
LOCATE.................................................................................................................................................. 8-22
USE DIN CELL........................................................................................................................................ 8-23
USE DOUT CELL.................................................................................................................................... 8-23
PGROUP VREF ...................................................................................................................................... 8-23
IPexpress Flow.......................................................................................................................................... 9-3
Single Port RAM (RAM_DQ) – EBR Based .............................................................................................. 9-7
True Dual Port RAM (RAM_DP_TRUE) – EBR Based ........................................................................... 9-13
Pseudo Dual Port RAM (RAM_DP) – EBR-Based.................................................................................. 9-22
Read Only Memory (ROM) – EBR Based............................................................................................... 9-25
First In First Out (FIFO, FIFO_DC) – EBR Based................................................................................... 9-28
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based.......................................................... 9-44
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based ............................................................ 9-46
Distributed ROM (Distributed_ROM) – PFU Based ................................................................................ 9-49
Initialization File Format .......................................................................................................................... 9-51
DATA_WIDTH......................................................................................................................................... 9-54
REGMODE.............................................................................................................................................. 9-54
RESETMODE ......................................................................................................................................... 9-54
CSDECODE............................................................................................................................................ 9-54
WRITEMODE.......................................................................................................................................... 9-54
GSR ........................................................................................................................................................ 9-54
DQS Grouping......................................................................................................................................... 10-2
DDR Software Primitives......................................................................................................................... 10-5
Memory Read Implementation ................................................................................................................ 10-9
Data Read Critical Path......................................................................................................................... 10-12
DQS Postamble .................................................................................................................................... 10-13
Memory Write Implementation .............................................................................................................. 10-14
Design Rules/Guidelines....................................................................................................................... 10-16
QDR II Interface .................................................................................................................................... 10-17
®
and Precision
4
®
RTL Synthesis ........................................................ 8-14
LatticeECP/EC Family Data Sheet
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