LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 368

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 15-9. MULTADDSUBSUM Mode Advance 1 Set-up
Targeting the sysDSP Block by Inference
The Inferencing flow enables the design tools to infer sysDSP Blocks from a HDL design. It is important to note that
when using the Inferencing flow; unless the code style matches the sysDSP Block results will not be optimal
results. Consider the following Veriflog and VHDL examples:
// This Verilog example will be mapped into single MULT9X9MAC with the output register enabled
// This will be mapped into single MULT9X9MAC with the output register enabled
module mult_acc (dataout, dataax, dataay, clk);
endmodule
output [16:0] dataout;
input [7:0] dataax, dataay;
input clk;
reg
wire [15:0] multa = dataax * dataay; // 9x9 Multiplier
wire [16:0] adder_out;
assign adder_out = multa + dataout; // Accumulator
always @(posedge clk)
begin
end
dataout <= adder_out; // Output Register of the Accumulator
[16:0] dataout;
15-7
LatticeECP-DSP sysDSP Usage Guide
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