LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 8

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Lattice ispTRACY Usage Guide
LatticeECP-DSP sysDSP Usage Guide
HDL Synthesis Coding Guidelines for Lattice Semiconductor FPGAs
SPI Compatible SPI Flash Vendors ............................................................................................................... 13-18
Technical Support Assistance........................................................................................................................ 13-18
Introduction ...................................................................................................................................................... 14-1
ispTRACY IP Core Features ............................................................................................................................ 14-1
ispTRACY IP Module Generator ...................................................................................................................... 14-1
ispTRACY Core Generator .............................................................................................................................. 14-2
ispTRACY Core Linker..................................................................................................................................... 14-4
ispTRACY ispLA Program................................................................................................................................ 14-6
Conclusion ....................................................................................................................................................... 14-9
References....................................................................................................................................................... 14-9
Technical Support Assistance.......................................................................................................................... 14-9
Introduction ...................................................................................................................................................... 15-1
sysDSP Block Hardware .................................................................................................................................. 15-1
sysDSP Block Software ................................................................................................................................... 15-2
sysDSP Blocks in the Report File .................................................................................................................. 15-10
Technical Support Assistance........................................................................................................................ 15-11
Appendix A. DSP Block Primitives ................................................................................................................. 15-12
Introduction ...................................................................................................................................................... 16-1
General Coding Styles for FPGA ..................................................................................................................... 16-1
Configuration Mode............................................................................................................................... 13-16
DONE Open Drain ................................................................................................................................ 13-16
DONE External...................................................................................................................................... 13-17
Master Clock Selection ......................................................................................................................... 13-17
Security ................................................................................................................................................. 13-17
Wake-up Sequence............................................................................................................................... 13-17
Wake-up Clock Selection ...................................................................................................................... 13-17
Bit Stream Compression ....................................................................................................................... 13-18
Overview ................................................................................................................................................. 15-1
Overview ................................................................................................................................................. 15-2
Targeting the sysDSP Block Using IPexpress ........................................................................................ 15-2
Targeting the sysDSP Block by Inference............................................................................................... 15-7
Targeting the sysDSP Block using Simulink ........................................................................................... 15-9
Targeting the sysDSP Block by Instantiating Primitives........................................................................ 15-10
MAP Report File.................................................................................................................................... 15-11
Post PAR Report File ............................................................................................................................ 15-11
MULT36X36 Primitive ........................................................................................................................... 15-12
MULT18X18 Primitive ........................................................................................................................... 15-12
MULT18X18MAC Primitive ................................................................................................................... 15-13
MULT18X18ADDSUB Primitive ............................................................................................................ 15-14
MULT18X18ADDSUBSUM Primitive .................................................................................................... 15-15
MULT9X9 Primitive ............................................................................................................................... 15-16
MULT9X9MAC Primitive ....................................................................................................................... 15-17
MULT9X9ADDSUB Primitive ................................................................................................................ 15-18
MULT9X9ADDSUBSUM Primitive ........................................................................................................ 15-19
Hierarchical Coding................................................................................................................................. 16-1
Design Partitioning .................................................................................................................................. 16-2
State Encoding Methodologies for State Machines ................................................................................ 16-3
Coding Styles for FSM ............................................................................................................................ 16-5
Using Pipelines in the Designs................................................................................................................ 16-6
Comparing IF statement and CASE statement ....................................................................................... 16-7
Avoiding Non-intentional Latches............................................................................................................ 16-8
7
LatticeECP/EC Family Data Sheet
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