LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 475

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

SPI Serial Flash Programming Using ispJTAG
Lattice Semiconductor
on LatticeECP/EC FPGAs
The INITN pin can be left open, connected to a microprocessor, status register, or other LatticeECP/EC devices.
Holding this pin low during configuration will keep the device from configuring. Do not tie this pin to a pull-down
resistor. There is a weak pull-up on this pin but if needed add an external 10K ohm pull-up resistor. This pin can
drive 8 mA. If driving an LED that requires higher current, use an external driver/buffer.
The DONE pin can be left open, connected to a microprocessor, status register, or other Lattice devices with
DONE pins. If you connect this pin to other DONE pins then all of the DONE pins in the chain will need to be set to
open drain (using ispLEVER or an attribute in your code) and a pull-up resistor of about 10K will need to be added.
Holding this pin low during configuration will keep the LatticeECP/EC from waking up. Do not tie this pin to a pull-
down resistor. There is a weak pull-up on this pin but, if needed, add an external 10K ohm pull-up resistor. This pin
can drive 8 mA. If driving an LED that requires higher current, use an external driver/buffer.
All of the SPI pins are part of I/O bank 3; therefore V
for bank 3 must be connected to the same voltage as the
CCIO
SPI Serial Flash.
When utilizing SPI Serial Flash, use of the SPI pins as user pins is generally not recommended. If you must use
one or more of the SPI pins as user I/O, do not change the I/O type or direction. For example, if, during configura-
tion, the SPI pin you wish to use is an input you may only use the pin as an input, not an output, and it must be of
type LVCMOS33.
If you set Config_Mode in the ispLEVER Preference Editor to SPI3, and you are instantiating the Soft IP, you will
get warnings when you compile your code. This is due to the Soft IP requiring use of the SPI3 port as normal I/O
during SPI Serial Flash programming. You can avoid these warnings by selecting None or JTAG instead of SPI3 for
the Config_Mode.
If you set Config_Mode to SPI3, or you instantiate the Soft IP into your code (assigning the SPI pins in the Prefer-
ence Editor or your code), the SPI pins will be protected from use by the Place and Route tools. If you set
Config_Mode to None or JTAG, and you are not instantiating the Soft IP, the SPI pins will not be protected from use
by the Place and Route tools. In this case, consider using the Prohibit Site “<pin number>” command on the SPI
pins to keep the Place and Route tools from using these pins. This is particularly useful if your design is I/O bound
and you want to allow Place and Route as much flexibility as possible. You can use the Package View in the Prefer-
ence Editor to place the Prohibits.
Try to select an SPI Serial Flash that is supported by your version of ispVM programming software. Check for the
latest SPI Serial Flash vendor support in the latest version of ispVM software. The ispVM software is available at no
charge from the Lattice web site at www.latticesemi.com. If your SPI Serial Flash is not supported on the latest
software, please contact Lattice Technical Support.
If you have selected a GPIO pin to drive the CCLK that is other than the pin recommended in Table 21-5 of this doc-
ument you will need to instantiate the Soft IP into your code. See the section above entitled “Including the SPI Inter-
face in the FPGA Design”.
Conclusion
By combining the new low cost LatticeECP/EC family of devices with low cost, third party serial Flash, engineers
can now take advantage of a very cost effective system solution. In addition to cost savings, the design also bene-
fits from the space conscious 8-pin package.
This new capability, in addition to the traditional configuration methods, is fully supported by the latest Lattice tools.
For more information on Lattice's family of devices, visit our web site at www.latticesemi.com.
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