LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 347

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Loading the Configuration Memory
Once the PROGRAMN and INITN pins are high, configuration can begin. Depending on the configuration mode
selected, data will be accepted on either the DI or D[0:7] pins on the rising edge of CCLK. If an error occurs at any
time during transfer of the data, the INITN pin will be driven low by the LatticeECP/EC device. For handshaking
configurations, the CSN or CS1N pin can be driven high to pause configuration and stop the Master clock. The
BUSY pin can be used by the LatticeECP/EC device to pause the configuration host EC/ECP. Once the full data
stream has been shifted in a CRC calculation done during configuration will be compared to the bit stream CRC. If
they match, the device will either proceed to the Wake-up sequence or overflow the next data to the next device. If
the CRC does not match, then the INITN pin will be driven low and the device will remain in configuration mode.
Wake Up the Device
When configuration is complete, the device will wake up in a predictable fashion. The following selections deter-
mine how the device will wake up. Two synchronous wake-up processes are available. One automatically wakes
the device up when the internal Done Bit is set even if the DONE pin is held low externally. The other waits for the
DONE pin to be driven high externally before starting the wake-up process. The DONE_EX preference determines
if the synchronous wake up will be controlled by the external driving of the DONE pin or ignores the external driving
of the DONE pin. Table 12-3 provides a list of the wake-up sequences supported by the devices.
Table 12-3. Wake-up Sequences supported by LatticeEC
Synchronous to Internal Done Bit
21 (Default)
Sequence
Default
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
1
2
3
4
5
6
7
8
9
DONE
DONE
DONE
DONE
DONE
DONE
DONE
Phase T0
GOE
GOE, GWDIS, GSR
GOE
GOE
GOE
GOE
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
GOE
GOE, GWDIS
GWDIS
GWDIS, GSR
GOE, GSR
GOE, GWDIS, GSR
GOE
GOE, GWDIS
GWDIS
GWDIS, GSR
GOE, GSR
Phase T1
12-14
GOE, GWDIS, GSR
GWDIS, GSR
GWDIS
GSR
GOE, GWDIS, GSR
GWDIS, GSR
DONE
DONE
DONE
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
GOE, GSR
GOE
GSR, GWDIS
GOE
GWDIS, GSR
GSR
GWDIS
LatticeECP/EC sysCONFIG Usage Guide
Phase T2
DONE
GOE, GWDIS, GSR
GWDIS, GSR
GSR
GWDIS
GOE, GWDIS, GSR
GOE
GWDIS, GSR
GOE, GWDIS, GSR
GWDIS, GSR
GSR
GOE, GSR
GOE
GWDIS
DONE
DONE
DONE
DONE
DONE
DONE
DONE
Phase T3