LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 399

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

July 2004
Introduction
Lattice Semiconductor’s ispLEVER
devices, provides options to help meet design timing and logic utilization requirements. Additionally, for those
instances where objectives push the capabilities of the device architecture, ispLEVER provides the tools for meet-
ing the most challenging requirements.
For the most aggressive design requirements, the designer should become familiar with a variety of timing con-
straints (called preferences) and Place And Route (PAR) techniques for providing the optimal PAR results as dis-
cussed in technical note number TN1018, Lattice Semiconductor Successful Place and Route.
If performance goals cannot be met with FPGA timing preferences and additional levels of the Place & Route
design process, improved performance can be achieved by directing the physical layout of the circuit in the FPGA.
This step, often referred to as floorplanning, is done by specifying FPGA location preferences.
This application note explains what floorplanning is, when it should be used, and how it is done with respect to Lat-
tice Semiconductor FPGA designs. This document is divided into four major sections:
Supported Architectures
Floorplanning can be done on all Lattice Semiconductor FPGA architectures.
Related Documentation
Designers are encouraged to reference the ispLEVER on-line documentation.
Floorplanning Definition
Floorplanning a digital logic design for implementation in a programmable device involves the physical or logical
partitioning of the design elements which results in a change in the physical placement or implementation of the
design elements. In other words, floorplanning is the grouping of design elements in a certain way to improve the
performance of a design.
With Lattice Semiconductor FPGAs, floorplanning is an optional methodology to help designers improve the perfor-
mance and density of a fully, automatically placed and routed design. Floorplanning is particularly useful in struc-
tured designs and data path logic. Design floorplanning is very powerful and provides a combination of automation
and user control for design reuse and modular, hierarchical, and incremental design flows.
Complex FPGA Design Management
Lattice Semiconductor FPGAs can implement large system designs that contain millions of gates, hundreds of
thousands of embedded memory bits, and intellectual property (IP) components. Design teams often work on large
designs. The design complexity requires EDA tools to manage and optimize the design. Large design management
is difficult, but performance optimization is even more difficult. Optimization requires many design iterations when
adding or modifying components. Complex, large system designs require the following:
www.latticesemi.com
• Floorplanning definition, logical and physical
• When to floorplan, general versus specific reasons
• How to floorplan: grouping constraints, examples, and Floorplanner GUI presentation
• Special considerations, large and special groupings
• The use of modular, hierarchical, or incremental design methods
• Software that makes management and optimization easier
®
software, together with Lattice Semiconductor’s catalog of programmable
16-1
Lattice Semiconductor
Design Floorplanning
Technical Note TN1010
tn1010_02.0