LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 362

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LFEC3E-3QN208I

Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r

Specifications of LFEC3E-3QN208I

Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
October 2005
Introduction
This technical note discusses how to access the features of the LatticeECP™-DSP sysDSP™ (Digital Signal Pro-
cessing) Block described in the LatticeECP/EC Family data sheet. Designs targeting the sysDSP Block offer signif-
icant improvement over traditional LUT-based implementations. Table 15-1 provides an example of the
performance and area benefits of this approach.
Table 15-1. sysDSP Block vs. LUT-based Multipliers
sysDSP Block Hardware
Overview
The sysDSP Blocks are located in a row at the center of the LatticeECP-DSP device. A sysDSP Block block dia-
gram is shown in Figure 15-1.
Figure 15-1. LatticeECP sysDSP Block Diagram
www.latticesemi.com
Input Registers from
SRO of left-side
sysDSP Block (or
tied to zero if none)
Intermediate
Pipeline Registers
Multiplier Width
Output
Registers
18x18
36x36
9x9
Note: Each sysDSP Block spans eight columns of PFUs.
36
Add/Sub (36) (9x9 ≤ 2x18) 1
9x9
PR0 (36)
Mult18-0
Input, Multiplier, Output
Input, Multiplier, Output
Input, Multiplier, Output
Accumulator (52) 1
In Reg A0
In Reg B0
Register Pipelining
9x9
Summation (38) (Two 20 Bits in 9x9 Mode)
9x9
PR1 (36)
Mult18-1
In Reg A1
In Reg B1
36x36 (Mult36)
9x9
In Reg A2
In Reg B2
9x9
Add/Sub (36) (9x9 ≤ 2x18) 3
15-1
LatticeECP LFECP20E-5
PR2 (36)
Mult18-2
Uses One DSP Block
f
235
211
177
Accumulator (52) 3
MAX
LatticeECP-DSP sysDSP
9x9
In Reg A3
In Reg B3
9x9
PR3 (36)
Mult18-3
LUTs
0
0
0
9x9
36
LatticeEC LFEC20E-5
f
Usage Guide
MAX
76
50
35
Uses LUTs
Adder, Subtractor and
Accumulator Functions
36x36, 18x18 and
9x9 Multiplier Functions
Output Registers to SRI
of right-side sysDSP Block
(if it exists)
Technical Note TN1057
LUTs
2225
174
608
tn1057_01.2

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