LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 431
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Appendix A. Example Extractions of Delays from Timing Reports
From the Set-up Report below, which was run for MAX conditions:
===============================================================
Preference: INPUT_SETUP PORT “ddr_dq_*” 2.000000 ns CLKNET “pll_nclk” ;
---------------------------------------------------------------------------------------------
------------------------------------
Passed:
pll_nclk +)
IN_DEL
ROUTE
NCLK_DEL
ROUTE
Logical Details:
Constraint Details:
Physical Path Details:
Destination: O-FF In
Source:
Data Path Delay:
Clock Path Delay:
Name
Name
• t
• t
• t
0.000ns delay ddr_dq_23 to ddr_dq_23 less
2.000ns offset ddr_dq_23 to clk (totaling -2.000ns) meets
6.206ns delay clk to ddr_dq_23 less
3.271ns feedback compensation less
3.195ns INREG_SET requirement (totaling -0.260ns) by 1.740ns
Data path ddr_dq_23 to ddr_dq_23:
Clock path clk to ddr_dq_23:
PD
FDS
FPGA_CLK
= 0.0 ns
The following path meets requirements by 1.740ns
= 3.195 ns
Fanout
Fanout
32 items scored, 0 timing errors detected.
---
---
136
(max) = 6.206 - 3.271 = 2.935 ns
1
--------
--------
Cell type
Delay (ns)
0.000
Delay (ns)
1.431
0.816
0.385
3.574
6.206
Port
0.000ns
6.206ns
Data in
LLHPPLL.CLKIN to
(0.0% logic, 0.0% route), 0 logic levels.
LLHPPLL.NCLK to
(29.3% logic, 70.7% route), 2 logic levels.
Pin type
AB4.INCK to
Pad
(0.0% logic, 0.0% route), 0 logic levels.
(29.3% logic, 70.7% route), 2 logic levels.
AB4.PAD to
U1_ddrct_np_o4_1_008/U3_databusif/ddr_dqoeZ0Z_23
Site
Site
18-9
Cell name
LLHPPLL.CLKIN clk_c
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
ddr_dq_23
AB4.INCK clk
N24.SC pll_nclk
for the DDR SDRAM Controller IP Core
(clock net +/-)
Resource
Resource
Board Timing Guidelines
(to
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