LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 363

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
sysDSP Blocks have three operating modes:
36x36 Mode
18x18 Mode
9x9 Mode
sysDSP Block Software
Overview
The sysDSP Block of the LatticeECP-DSP device can be targeted in a number of ways.
Targeting the sysDSP Block Using IPexpress
IPexpress allows you to graphically specify sysDSP elements. Once the element is specified, an HDL file is gener-
ated which can be instantiated in a design. IPexpress allows users to configure all ports and set all available
parameters. The following show modules which target the sysDSP Block. For design examples using IPexpress,
refer to EXAMPLES in your ispLEVER software. From the Project Navigator pull-down menu, go to File -> Open
Example). The following four element types can be specified via IPexpress:
• One 36x36 multiplier
• Four Multipliers
• Two 52-bit MACs
• Two sums of two 18x18 multipliers each
• One sum of four 18x18 multipliers
• Eight Multipliers
• Two 34-bit MACs
• Four sums of two 9x9 multipliers each
• Two sums of four 9x9 multipliers each
• IPexpress™ in the Lattice ispLEVER
• The coding of certain functions into a design’s HDL allows the synthesis tools to inference the use of a sys-
• The implementation of designs in Mathwork’s Simulink tool using a Lattice Block set. The ispLEVER sys-
• Instantiation of sysDSP primitives directly in the source code.
• MULT (Multiplier)
• MAC (Multiplier Accumulate)
• MULTADDSUB (Multiplier Add/Subtract)
• MULTADDSUBSUM (Multiply Add/Subtract and SUM)
DSP elements. These modules can then be used in HDL designs as appropriate.
DSP Block.
DSP portion of the ispLEVER tools then converts these blocks into HDL as appropriate.
®
design tools allows the rapid creation of modules implementing sys-
15-2
LatticeECP-DSP sysDSP Usage Guide
