LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 78

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Signal Descriptions (Cont.)
TDI
TDO
V
Configuration Pads (used during sysCONFIG)
CFG[2:0]
INITN
PROGRAMN
DONE
CCLK
BUSY/SISPI
CSN
CS1N
WRITEN
D[7:0]/SPID[0:7]
DOUT/CSON
DI/CSSPIN
CCJ
Signal Name
I/O
I/O
I/O
I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
I/O Read control command in SPI3 or SPIX mode.
I/O sysCONFIG Port Data I/O.
I/O
—
O
O
I
I
I
I
I
I
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
Output pin. Test Data out pin used to shift data out of device using 1149.1.
V
Mode pins used to specify configuration modes values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
Write Data on Parallel port (Active low).
Output for serial configuration data (rising edge of CCLK) when using sys-
CONFIG port.
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. Output when used in
SPI/SPIX modes.
CCJ
- The power supply pin for JTAG Test Access Port.
4-2
LatticeECP/EC Family Data Sheet
Description
Pinout Information