LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 346

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
that User Mode read/write operations from/to the EBR and distributed RAM do not interfere with the transparent
read back.
Boundary Scan and BSDL Files
The LatticeECP/EC BSDL files can be found on the Lattice Semiconductor web site. The boundary scan ring will
cover all the I/O pins, dedicated and dual-purpose sysCONFIG pins. The sysCONFIG pins can be observed using
the Boundary Scan.
Configuration Flow
The writing to the configuration SRAM memory can generally be split into three phases.
1. Clear the configuration memory. 
2. Load configuration data into the memory. 
3. Wake up the device.
The Wake-up sequence puts the device into functional mode after full configuration. Choosing a proper Wake-up
sequence is important, to prevent contention.
The following sections describe the three steps to configure LatticeECP/EC devices.
Clearing the Configuration Memory
Two possible methods can clear the internal configuration memory of the LatticeECP/EC device. The first is when
the device powers up, the second is by toggling the PROGRAMN pin.
Power-up Sequence
On power-up the device tri-states all the I/Os, sets them to LVCMOS type, and sets the INITN and DONE pin to low.
The device prepares for configuration by resetting the configuration circuitry, clearing the DONE bit and CRC regis-
ters. The device clears the configuration memory, including I/O options such as PCI clamp, and gets ready to start
configuration. The JTAG port is ready to be used as soon as the device clears the configuration memory.
After the device clears the POR, the device samples the Configuration Mode pins CFG[0:2] and recovers the rele-
vant configuration pins according to the Configuration Mode pin settings. The device will then release the INITN pin
if the PROGRAMN pin is high. If a Master Mode is selected, the device starts driving the master clock out of the
CCLK pin. The INITN pin can be driven low externally to delay device configuration. Once the INITN pin goes high,
the device is ready for configuration to start.
Toggling the PROGRAMN Pin
After a device is powered up, toggling the PROGRAMN pin will initiate a sequence to prepare the LatticeECP/EC
device for re-configuration from an external memory source. Upon driving the PROGRAMN pin low, the INITN and
DONE pins will drive low, the memory will start clearing, and the I/O pins will become tri-stated and pulled up to
V
Upon driving the PROGRAMN pin high, the CFG[0:2] are sampled to determine the configuration mode to imple-
ment as well as which configuration pins will be used for configuration. If a master mode is selected, CCLK will be
driven. The INITN pin will be released once the configuration memory is cleared and the PROGRAMN pin is driven
high. Holding the INITN pin low will delay configuration. Configuration will begin as soon as the INITN pin is
released and pulled high.
CCIO.
After power-up or toggling the PROGRAMN pin low, the configuration memory is cleared automatically. The
INITN pin is driven high by the EC/ECP device when the device has finished clearing the configuration memory
and Done bit. The INITN pin can also be driven externally by the user to delay the configuration process.
Loading the bit stream from DI or D[0:7], depending on the selected configuration mode. The INITN pin is set to
low on any error and BUSY can be used to delay configuration
12-13
LatticeECP/EC sysCONFIG Usage Guide