LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 342

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Figure 12-4. Simple SPIX Example with OP CODE Resistors
Master Serial Mode
Configuration of the LatticeECP/EC device in Master Serial mode will drive the CCLK signal out to the Slave Serial
devices in the chain and the SPROM that will provide the serial bit stream. The device accepts the data at DI on the
rising edge of CCLK. The Master Serial device starts driving CCLK after INITN transitions from low to high and
continues to drive the CCLK until the external DONE pin is driven high and one hundred plus clock cycles have
been generated. The CCLK frequency on power-up defaults to 2.5MHz. The master clock frequency default
remains until the new clock frequency is loaded from the bit stream into the device.
If a Master Serial device is daisy chained with other serial devices, once the master device is fully configured, the
bypass option will take effect. As additional data is presented to the Master DI pin, the data will be bypassed to the
next device on the DOUT pin.
Figure 12-5 shows a master serial daisy chain. The daisy chain method allows multiple Lattice FPGA devices to be
configured together. The first device in the daisy chain operates in Master Serial Mode with the Bypass option,
while the other Lattice FPGA devices in the daisy chain operate in Slave Serial Mode.
Master Serial (no overflow option)
Master Serial (Bypass ON)
Mode
OP CODE E8)
SPI Flash
(with
*SPID0 connects to SO and resistor.
SCK
SO
CS
SI
CFG[2]
10K
10K
10K
10K
10K
10K
10K
10K
1
1
CCLK
CSSPIN
SISPI
SPID0*
SPID7
SPID6
SPID5
SPID4
SPID3
SPID2
SPID1
SPID0*
PROGRAMN
CFG[1]
12-9
0
0
Lattice FPGA
SPIX
LatticeECP/EC sysCONFIG Usage Guide
CFG[0]
0
0
DONE
CFG2
CFG1
CFG0
INITN
MASTER_SERIAL
MASTER_SERIAL_BYPASS
CONFIG_MODE Parameter